AMD’s next-generation Radeon RX 7000 graphics cards are set to launch in the second half with improved ray-tracing capabilities and a significantly higher shader count. Much of this will be achieved using an MCM or chip-based design paired with TSMC’s state-of-the-art 5nm process node. One of AMD’s senior engineers (Brian Walters) inadvertently dropped some of the specifications of the Navi 31, 32 and 33 matrices (now deleted). These dies are designed to power the Radeon RX 7900 XT, 7800 XT, 7700 XT and 7600 XT:
According to his biography, the high end The Navi 31 die (the mother die for the Radeon RX 7900 XT, 7800 XT and 7800) will take advantage of TSMC’s 5nm and 6nm nodes. This lines up with what has been reported by @Greymon55 (on Twitter) in the past. A mockup of the MCM design can be seen below. Here, Navi 31 and Navi 32 die adopt dual chip design. The Radeon RX 7900 XT will pack up to 15,360 shaders on 60 workgroup processors (WGP) paired with 16GB of GDDR6 memory on a 256 goal bus. The “Infinity” L3 cache will be increased to 256 MB, 3D stacked on the main compute die. The GPU core will run at around 2.5GHz, like Navi 21, which is a bit of a surprise if it’s made on TSMC’s N5 node (maybe N6 to improve sourcing). Overall, Navi 31 should easily be 2.2-2.5 times faster than its predecessor, with the RX 7800 XT beating the RX 6800 XT by up to 50%.
Each Graphics Die (GCD) has three Shader Engines each consisting of two Shader Arrays. In turn, each Shader Array contains five WGPs containing eight SIMD units (against four on RDNA 2). The two fabrics are connected by a bridge interconnect associated with 256 MB of “Infinity” L3 cache. According to the source, the GCDs will be fabricated on TSMC’s 5nm (N5) node while MCD will be fabricated on the older 6nm (N6) node. Each dice should come with a 128-bit bus (divided into eight controllers), resulting in an overall bus width of 256-bit and the same external bandwidth of 448 GB/s as the RX 6800 XT/6900XT.
AMD’s RDNA 3 graphics architecture is set to get a major front-end overhaul, with redesigned workgroup processors in place of compute units or dual compute units. With RDNA 1 and 2, WGPs were the basic units for workload planning (from CUs on GCN/Vega), but it looks like this will change again with Navi 3x. Dual compute units are dropped in favor of larger workgroup processors, packing up to 256 stream processors across eight 32-width SIMDs. This means that the wave32 programming format will be retained, but the number of global active waves will be increased.
Navi 32 is also going to be a chiplet design with two calculation matrices and an MCD. It will power the Radeon RX 7700 XT. We’re looking at a core count of around 10,240 shaders (or 40WGP) and a 192-bit bus width paired with 12GB of GDDR6 memory. The L3 “Infinity Cache” will most likely be reduced to 192MB 3D stacked on top of the compute array. The GPU core will operate between 2.6 and 2.8 GHz. The Radeon RX 7700 XT should be around 1.5-2x faster than the 6700 XT, with about the same power consumption. Like Navi 31, it will be manufactured on TSMC’s 5nm and 6nm process nodes.
Finally, we have the Navi 33 die. It will have 4096 shaders (stream processors) across 16 WGPs. It should power the Radeon RX 7600 XT, making it a massive upgrade over the existing Radeon RX 6600 XT and its 2,304 shaders. What is interesting is that this The GPU core is configured to run on TSMC’s N6 node only which is essentially a refresh of node N7. This makes it possible for the Radeon RX 7600 XT (which will be based on this die) to be a refresh as well.